This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-320007, filed Nov. 10, 1999; and No. 2000-164692, filed Jun. 1, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a failure analyzing apparatus and a failure analyzing method for a semiconductor integrated circuit, which specify or localize the location of a failure (hereinafter referred to as xe2x80x9cfailure locationxe2x80x9d) by using an emission image formed by hot electrons that are emitted from the surface of a semiconductor integrated circuit chip.
Due to the recent ever-improving scale and integration density of very large scale semiconductor integrated circuits (VLSIs), it has become significantly important to develop the technique of specifying failure locations and shorten the analyzing time.
The typical analysis on the function failure of a VLSI is a failure location specifying scheme which uses a simulator and electron beam (EB) tester.
This conventional scheme using a simulator and EB tester establishes a link to a CAD (Computer Aided Design) unit, generates a failure dictionary and narrows down probe points based on the results of the actual simulation analysis and failure simulation results, and then performs failure analysis by actually using a simulator and EB tester. The conventional scheme therefore requires a significant amount of pre-analysis processing, which is likely to increase the time needed to specify a failure location.
There is a standby EMS (Emission Micro Scope) scheme which holds a device, such as a semiconductor integrated circuit chip, in a standby state or a stable operational state, integrates hot electrons that are generated from a failure location to acquire an emission image, and specifies the failure location based on the emission image.
This scheme cannot however accomplish EMS analysis on dynamic type products which are not easily held at a stable operational state and analog-mixed products that have a circuit in which a through current always flows.
In short, the conventional failure analyzing apparatus and method that use a simulator and EB tester undesirably requires a long time for specifying a failure location. Further, the conventional failure analyzing apparatus and method that employ the standby EMS scheme cannot perform failure analysis on dynamic type products and analog-mixed products.
Accordingly, it is an object of the present invention to provide a failure analyzing apparatus and failure analyzing method for a semiconductor integrated circuit, which can shorten the time needed to specify a failure location and can perform failure analysis on dynamic type products and analog-mixed products.
It is another object of this invention to provide a failure analyzing apparatus for a semiconductor integrated circuit which can specify a real failure location.
To achieve the above objects, according to one aspect of this invention, there is provided a failure analyzing apparatus for a semiconductor integrated circuit, which comprises a test signal generating section for generating test signals for operating a semiconductor integrated circuit chip; an emission image detecting section for detecting an emission image formed by hot electrons emitted from a good semiconductor integrated circuit chip and an emission image formed by hot electrons emitted from a target semiconductor integrated circuit chip to be subjected to failure analysis, both chips being operable upon reception of the test signal; and an image processing section, connected to the emission image detecting section, for specifying a failure location in the target semiconductor integrated circuit chip based on both emission images detected by the emission image detecting section.
According to another aspect of this invention, there is provided a failure analyzing method for a semiconductor integrated circuit, which comprises the steps of operating a good semiconductor integrated circuit chip and a target semiconductor integrated circuit chip to be subjected to failure analysis by supplying test signals to the good semiconductor integrated circuit chip and the target semiconductor integrated circuit chip from a testing device; detecting an emission image formed by hot electrons emitted from the good semiconductor integrated circuit chip and an emission image formed by hot electrons emitted from the target semiconductor integrated circuit chip by using an emission analyzer; and specifying a failure location in the target semiconductor integrated circuit chip by performing image processing on both emission images detected.
According to a further aspect of this invention, there is provided a failure analyzing apparatus for a semiconductor integrated circuit, which comprises a function tester for generating test signals and supplying the test signals to a semiconductor integrated circuit chip to execute a function test thereof; an emission analyzer for detecting an emission image formed by hot electrons emitted from the semiconductor integrated circuit chip when the function test is performed by the function tester; an image processing device, connected to the emission analyzer, for specifying a failure location in a target semiconductor integrated circuit chip to be subjected to failure analysis, based on an emission image of a good semiconductor integrated circuit chip detected by the emission analyzer and an emission image of the target semiconductor integrated circuit chip; and a display device, connected to the image processing device, for displaying the failure location specified by the image processing device.
According to a still further aspect of this invention, there is provided a failure analyzing apparatus for a semiconductor integrated circuit, which comprises a function tester for generating supply voltages and test signals and supplying the supply voltages and the test signals to a semiconductor integrated circuit chip to execute a function test thereof; an emission analyzer for detecting an emission image by integrating hot electrons emitted from the semiconductor integrated circuit chip when the function test is performed by the function tester, an integration time for the hot electrons being variable; an image processing device, connected to the emission analyzer, for specifying a failure location in a target semiconductor integrated circuit chip to be subjected to failure analysis, based on an emission image of a good semiconductor integrated circuit chip detected by the emission analyzer and an emission image of the target semiconductor integrated circuit chip; a display device, connected to the image processing device, for displaying the failure location specified by the image processing device; and a condition providing device for altering an operational condition by variously changing at least a value of the supply voltages generated by the function tester and/or the integration time for hot electrons in the emission analyzer, causing the function tester to operate the target semiconductor integrated circuit chip in each alteration to check a number of occurrences of false emission caused by emission images detected by the emission analyzer, and acquiring that operational condition under which the number of occurrences of false emission becomes equal to or smaller than a predetermined value, whereby an operation of the function tester and/or an operation of the emission analyzer is controlled based on the operational condition acquired by the condition providing device.
According to a yet still further aspect of this invention, there is provided a failure analyzing apparatus for a semiconductor integrated circuit, which comprises a function tester for generating supply voltages and test signals and supplying the supply voltages and the test signals to a semiconductor integrated circuit chip to execute a function test thereof; an emission analyzer for detecting an emission image by integrating hot electrons emitted from the semiconductor integrated circuit chip when the function test is performed by the function tester, an integration time for the hot electrons being variable; an image processing device, connected to the emission analyzer, for specifying a failure location in a target semiconductor integrated circuit chip to be subjected to failure analysis, based on an emission image of a good semiconductor integrated circuit chip detected by the emission analyzer and an emission image of the target semiconductor integrated circuit chip, and outputting coordinate data of the failure location; a display device, connected to the image processing device, for displaying the failure location specified by the image processing device; a condition providing device for altering an operational condition by variously changing at least a value of the supply voltage generated by the function tester and/or the integration time for hot electrons in the emission analyzer, causing the function tester to operate the target semiconductor integrated circuit chip in each alteration to check a number of occurrences of false emission caused by emission images detected by the emission analyzer, and acquiring that operational condition under which the number of occurrences of false emission becomes equal to or smaller than a predetermined value, whereby an operation of the function tester and/or an operation of the emission analyzer is controlled based on the operational condition acquired by the condition providing device; a navigation device, connected to the image processing device, for storing net data and coordinate data of the target semiconductor integrated circuit chip and generating node data and coordinate data which are associated with a node of a preceding circuit of a node corresponding to the coordinate data output from the image processing device; a potential measuring device, connected to the navigation device, for measuring a potential of a surface of the semiconductor integrated circuit at a position corresponding to the coordinate data generated by the navigation device; a potential comparing device, connected to the potential measuring device and the navigation device, for storing expected value data of potentials at all nodes of the target semiconductor integrated circuit chip and comparing the potential measured by the potential measuring device with an expected value of a node corresponding to the node data provided by the navigation device; and a coordinate data outputting device, connected to the potential comparing device, for outputting coordinate data of the node corresponding to the node data provided by the navigation device to the display device as coordinate data corresponding to a failure location in the target semiconductor integrated circuit chip when the potential measured by the potential measuring device does not match with the expected value of the node corresponding to the node data provided by the navigation device.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.